`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/01/06 14:28:34
// Design Name: 
// Module Name: tb_frv_soc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_frv_soc(

    );
reg clk;
reg rst_n;

logic [4:0] button_in_0;
logic       rxd_0      ;
logic       rxd_1      ;
logic [15:0]switch_in_0;
logic [7:0] din        ;
logic       start      ;

wire [3:0]  dig_0      ;
wire        pwm_0      ;
wire [7:0]  seg_0      ;
wire        txd_0      ;
wire        txd_1      ;

wire        uart0_tx   ;

wire veri_uart_vld;
wire[7:0] veri_uart_rx_data;


always begin
    #1;
    clk=~clk;
end

initial begin 
button_in_0=5'b0000;
switch_in_0=16'h0000;
din        =0;
start      =0;

clk=0;
rst_n=1;
#1;
rst_n=0;
#3;
rst_n=1;

for (int i = 0; i < 20; i++) begin
    din        <= 8'h48;
    start      <=1;
    @(posedge clk);
    start      <=0;
    repeat(5000) @(posedge clk);    
end


end

    uart_tx #(
            .DIV(50),
            .PARITY(0)
        ) inst_uart_tx (
            .clk   (clk),
            .rst   (~rst_n),
            .din   (din),
            .start (start),
            .tx    (rxd_0),
            .busy  ()
        );


uart_rx #(
    .DIV(50),
    .PARITY(0)
)uart_rx_inst(
    .clk        (clk),
    .rst        (~rst_n),
    .rxd        (uart0_tx),
    .dout       (veri_uart_rx_data),
    .dout_valid (veri_uart_vld),
    .par_err    (), // 这个是奇偶校验的结果
    .busy       () //这个可以作为一个正在接收的状态位，但是我没有进行使用
);

frv_soc_top #(
    .UDIV(50)
)_frv_soc_top(
.clk             (clk),
.rst_n           (rst_n),
.uart0_rx        (rxd_0),
.uart0_tx        (uart0_tx),
.swc_vec         (switch_in_0),
.btn_vec         (button_in_0),
.seg             (seg_0),
.dig             (dig_0)
);



endmodule
